View LC7153M_319252.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number:ENN4160A
CMOS IC
LC7153, 7153M
Universal Dual-PLL Frequency Synthesizers
Overview
The LC7153 and LC7153M are universal dual-PLL frequency synthesizers for use in cordless telephone applications in the USA, South Korea and Australia, and satellite broadcast tuners in the USA and Europe. The LC7153 and LC7153M both have two PLLs with a 16-bit programmable divider to generate a 1.5 to 160MHz local-oscillator frequency, and a phase detector. They also have a dual charge pump and fast lock-up circuitry for rapid PLL locking when changing frequency, an unlock indication output and an uncommitted output under external control. The PLLs share a 14-bit divider to generate a 320Hz to 640kHz reference frequency using a 10.24MHz crystal. The LC7153 and LC7153M can be controlled from an ex2 ternal microcontroller using a C B serial interface. They also have a standby mode for single PLL operation. The LC7153 and LC7153M operate from a 4.0 to 5.5V supply. The LC7153 is available in 24-pin DIPs, and the LC7153M, in 24-pin MFPs.
Package Dimensions
unit:mm 3067A-DIP24S
[LC7153]
21.0 24 13
7.62 6.4
1 0.9
12
(0.71)
1.78
0.48
0.95
0.51min
unit:mm 3112A-MFP24S
[LC7153M]
Features
* Dual charge pump and fast lock-up circuitry for rapid PLL locking. * PLL unlock indication. * 16-bit programmable local-oscillator divider. * 1.5 to 160MHz local-oscillator frequency (VDD=4.0 to 5.5V). * 14-bit programmable reference-frequency divider. * 320Hz to 640kHz reference frequency using a 10.24MHz crystal. * LPF transistor. 2 * C B serial interface. * 4.0 to 5.5V supply. * 24-pin DIP (LC7153) and 24-pin MFP (LC7153M)
* CCB is a trademark of SANYO ELECTRIC CO., LTD. * CCB is SANYO's original bus format and all the bus addresses are controlled by SANYO.
24
13
5.4
3.3 3.9max
(3.25)
SANYO : DIP24S
12.5
0.15
0.35
1.0
0.1 1.5
(0.75)
SANYO : MFP24S
Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges,or other parameters) listed in products specifications of any and all SANYO products described or contained herein.
SANYO Electric Co.,Ltd. Semiconductor Company
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
73101TN (KT)/33195TH (ID)/9302JN No.4160-1/11
0.63
1
12
1.7max
7.6
0.25
LC7153, 7153M
Pin Assignment
Block Diagram
No.4160-2/11
LC7153, 7153M
Pin Functions
Number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Name XIN CE CL DI LDB LDA CA TEST PDA2 PDA1 AIA AOA OUTA PIA VSS PIB VD D CB OUTB AOB AIB PDB1 PDB2 XOUT Crystal oscillator input Chip enable input Clock input Serial data input PLLB unlock-detector output PLLA unlock-detector output Fast lock-up capacitor A connection Test input PLLA phase-detector secondary output PLLA phase-detector main output LPF transistor A input LPF transistor A output Uncommitted output A PLLA local-oscillator input Ground PLLB local-oscillator input 5V supply Fast lock-up capacitor B connection Uncommitted output B LPF transistor B output LPF transistor B input PLLB phase-detector main output PLLB phase-detector secondary output Crystal oscillator output Function
Specifications
Absolute Maximum Ratings at Ta = 25C
Parameter Supply voltage range CE, CL, DI, AIA and AIB input voltage range XIN, PIA, PIB, CA, CB and TEST input voltage range LDA, LDB, OUTA and OUTB output current range AOA and AOB output current range CA and CB output current range LDA and LDB output voltage range AOA, AOB, OUTA and OUTB output voltage range PDA1, PDA2, PDB1, PDB2, CA, CB and XOUT output voltage range Allowable power dissipation Operating temperature Storage temperature Symbol VDD VI1 VI2 IO1 IO2 IO3 VO1 VO2 VO3 Pd max Topr Tstg LC7153 LC7153M Conditions Ratings -0.3 to +7.0 -0.3 to +7.0 -0.3 to VDD+0.3 0 to 3 0 to 6 0 to 1 -0.3 to +7.0 -0.3 to 15.0 -0.3 to VDD+0.3 350 240 -40 to +85 -55 to +125 Unit V V V mA mA mA V V V mW mW C C
(Note) Pins PIA, PIB, CA and CB have a weaker electrostatic breakdown strength than the other pins.
Recommended Operating Conditions at Ta = 25C
Parameter Supply voltage Supply voltage range Symbol VDD VDD Conditions Ratings 5 4.0 to 5.5 Unit V V
No.4160-3/11
LC7153, 7153M
Electrical Characteristics at Ta = -40 to +85C, VDD=4.0 to 5.5V, VSS=0V, unless otherwise noted.
Parameter Symbol Conditions VDD=4.5V, fI=60MHz. See note 1. VDD=5.5V, fI=160MHz. See note 1. VDD=4.5V, fI=60MHz. See note 2. VDD=5.5V, fI=160MHz. See note 2. CE, CL and DI low-level input voltage CE, CL and DI high-level input voltage PDA1 and PDB1 low-level output voltage PDA2 and PDB2 low-level output voltage LDA, LDB, OUTA and OUTB low-level output voltage AOA and AOB low-level output voltage PDA1 and PDB1 high-level ouput voltage PDA2 and PDB2 high-level ouput voltage LDA and LDB output voltage AOA, AOB, OUTA and OUTB output voltage CA and CB output voltage CA and CB low-level threshold voltage CA and CB high-level threshold voltage CE, CL and DI low-level input current XIN low-level input current PIA and PIB low-level input current AIA and AIB low-level input current TEST low-level input current CE, CL and DI high-level input current XIN high-level input current PIA and PIB high-level input current AIA and AIB high-level input current TEST high-level input current LDA and LDB output leakage current PDA1, PDB1, PDA2 and PDB2 output leakage current AOA, AOB, OUTA and OUTB output leakage current CA and CB output leakage current CA and CB source current Fast lock-up mode 0 CA and CB sink current Fast lock-up mode 1 CA and CB sink current Fast lock-up mode 2 CA and CB sink current Fast lock-up mode 3 CA and CB sink current XIN input frequency PIA and PIB input frequency XIN rms input amplitude PIA and PIB rms input amplitude Crystal oscillator frequency XIN internal feedback resistor PIA and PIB internal feedback resistor TEST internal pull-down resistor XIN, PIA and PIB input capacitance VIL1 VIH1 VOL1 VOL2 VOL3 VOL4 VOH1 VOH2 VO1 VO2 VO3 VT- VT+ IIL1 IIL2 IIL3 IIL4 IIL5 IIH1 IIH2 IIH3 IIH4 IIH5 IOFF1 IOFF2 IOFF3 IOFF4 IS1 IS2(0) IS2(1) IS2(2) IS2(3) fI1 fI2 VI1 VI2 fXTAL Rf1 Rf2 Rd CI VI=0V VI=0V, VDD=5.0V VI=0V, VDD=5.0V VI=0V VI=0V, VDD=5.0V VI=5.5V VI=5.0V, VDD=5.0V VI=5.0V, VDD=5.0V VI=5.0V VI=5.0V, VDD=5.0V VO=5.5V VO=0 or 5.5V VO=13V VO=0 V or VDD VO=0V, VDD=5.0V VO=3.0V, VDD=5.0V VO=3.0V, VDD=5.0V VO=3.0V, VDD=5.0V VO=3.0V, VDD=5.0V Capacitively coupled sine wave Capacitively coupled sine wave, VDD=5.0V Capacitively coupled sine wave Capacitively coupled sine wave CI50. See note 3. VDD=5.0V VDD=5.0V VDD=5.0V -95 -190 0.01 3.5 6.0 0.01 160 5.0 10.0 5.0 100 -380 3.5ls2(3) 4.0ls2(3) 4.5ls2(3) 2.5ls2(3) 3.0ls2(3) 3.4ls2(3) 1.5ls2(3) 2.0ls2(3) 2.4ls2(3) 18 1 1.5 100 70 4.0 10.24 0.7 430 30 6.0 35 70 13 160 800 800 13.0 3.5 6.0 0.01 IO=1mA IO=2mA IO=2mA IO=0.5mA, VAIA=VAIB=1.2V IO=1mA, VAIA=VAIB=1.3V IO=1mA IO=2mA 0 0 0 VDD-1 VDD-1 0 0 0 0.5VDD 5.0 11 18.0 10.0 5.0 5.0 11.0 18.0 10.0 5.5 13.0 VDD 0.2VDD 0 2.2 Ratings min typ 9.0 20.0 5.0 11.0 max 18.0 40.0 10.0 22.0 0.8 5.5 1.0 1.0 1.0 0.5 0.5 Unit mA mA mA mA V V V V V V V V V V V V V V A A A nA A A A A nA A A nA A nA A A A A A MHz MHz mV mV MHz M k k pF
Supply current
IDD
Notes 1. Dual PLL, both PLLA and PLLB operating, SB=0, fXTAL=10.24MHz, VPIA=VPIB=70mV, all other inputs=0V, all outputs open. 2. Standby mode, PLLB stopped, SB=1, fXTAL=10.24MHz, VPIA=70mV, all other inputs=0V, all outputs open. 3. CI in the crystal impedance. Contact Nihon Denpa Kogyo for further information.
No.4160-4/11
LC7153, 7153M
Serial Data Input Timing
Parameter Data setup time Data hold time LOW-level chip enable time Chip enable setup time Chip enable hold time LOW-level clock pulsewidth HIGH-level clock pulsewidth Chip enable to data latch time
Symbol tSU tHD tEL tES tEH tCL tCH tLA 10.24MHz crystal
Conditions
Ratings min 400 4/fXTAL 400 4/fXTAL 400 4/fXTAL 400 4/fXTAL 400 4/fXTAL 400 4/fXTAL 400 4/fXTAL 400 4/fXTAL max
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Other crystal frequencies 10.24MHz crystal Other crystal frequencies 10.24MHz crystal Other crystal frequencies 10.24MHz crystal Other crystal frequencies 10.24MHz crystal Other crystal frequencies 10.24MHz crystal Other crystal frequencies 10.24MHz crystal Other crystal frequencies 10.24MHz crystal Other crystal frequencies
Functional Description PLLA and PLLB Programmable Dividers PLLA and PLLB input frequency ranges are set by Mode 2 command bits FA and FB, respectively. Their divider ratios, NA and NB, are set by Mode 1 command bits DA0 to DA15 and DB0 to DB15, respectively. Programmable Reference Divider The divider ratio, NR, is set by Mode 2 command bits R0 to R13. The reference frequency is given by fXIN/(2xNR). Phase Detector The state of the phase-detector output as a function of the divider ratio and reference frequency is shown in table 1. Table 1. Phase-detector output states
Condition fI/N > fref fI/N < fref fI/N = fref PDA1, PDB1 HIGH LOW HIGH impedance
When PLLA is unlocked, LDA is pulled LOW and both PDA1 and PDA2 are active. PLLB operates identically to PLLA. Mode 2 command bits UL0 and UL1 set the unlock phase-error threshold, and bits UE0 and UE1, the LDA and LDB output extension. Dual Charge Pump A typical dual charge-pump configuration is shown in figure 1. The phase-detector secondary output is active after a change in frequency, and the phase error causes the PLL to unlock. In this case, the load resistance R1 becomes R1M||R1S, decreasing the LPF time constant and the time required to lock the PLL.
Note N=NA for PLLA, and NB for PLLB
No.4160-5/11
LC7153, 7153M
Figure 1. Dual charge-pump circuit The phase-detector secondary output is high impedance when the PLL is locked. In this case, R1 becomes R1M, Test Mode TEST should be LOW or open for normal operation. Serial Input Data Serial data should be input only after fXIN has become stable. Mode 1 command format and functions The Mode 1 command comprises the data bits which determine the PLLA and PLLB programmable divider ratios. increasing the LPF time constant and improving sideband and modulation response.
The command format is shown in figure 2. Bits DA0 to DA15 and DB0 to DB15 determine the PLLA and PLLB programmable divider ratios, respectively. Bit DA0 is the first bit received. The range of allowable divider ratios is N =256 (0100H) to 65535 (FFFFH).
Figure 2. Mode 1 command (programmable divider data)
No.4160-6/11
LC7153, 7153M
Mode 2 command format and functions The Mode 2 command comprises the data bits which determine the reference frequency divider ratio and control functions. The command format is shown in figure 3. Bit R0 is the first bit received.
Figure 3. Mode 2 command (reference divider and control data) Bits R0 to R13 determine the reference divider ratio. The range of allowable divider ratios is NR=8 (0008H) to 16383 (3FFFH). Bits FL0 and FL1 are the fast lock-up mode select bits. The fast lock-up modes are shown in table 2. The higher the mode number, the greater the expansion width of the detected phase error signal.
FL0 0 1 0 1 FL1 0 0 1 1 Fast lock-up mode 0 1 2 3
Figure 4. Fast lock-up operating modes Bit SB is the standby mode control bit. When SB=1, standby mode is selected. In standby mode, PLLB is stopped, PIB is pulled LOW, and PDB1 and PDB2 are high impedance. When SB=0, normal operation is selected. Bits UL0 and UL1 determine the unlock detection threshold. The PLL unlock detector output, LDA or LDB, is pulled LOW when the phase differential between the reference and the divider inputs exceeds the threshold set by UL0 and UL1. The threshold for different crystal frequencies is shown in table 4, and the threshold for other frequencies can be calculated. The threshold is common to both PLLs. Note that a PLL will temporarity lose lock when either UL0 or UL1 is changed.
Bits OA and OB are the uncommitted output control bits. They are latched and then inverted to control OUTA and OUTB, respectively. If either bit is 1, the open-drain output is pulled LOW. Bits FA and FB are the input frequency range select bits. The PIA and PIB frequency ranges, set by FA and FB, respectively, are shown in table 3. Table 3. Frequency ranges
FA, FB 0 1 Input frequency range 1.5 to 40.0 35 to 160 Unit MHz MHz
Bits HSA, HSB and HSM are the fast lock-up control bits. When HSA or HSB=1, the fast lock-up circuits for PLLA or PLLB, respectively, are ON. When HSA or HSB=0, the respective circuits are OFF. For use with FM, the fast lockup circuits should be OFF. HSM determines the fast lockup operating mode. When HSM=0, operating mode 0 is selected and the fast lock-up only operates when the PLLs are unlocked. When HSM=1, operating mode 1 is selected and the fast lock-up operates normally, as shown in figure 4.
No.4160-7/11
LC7153, 7153M
Table 4. Unlock detector thresholds
UL0 0 1 0 1 UL1 0 0 1 1 LDA, LDB phase error threshold 0 4/fXIN 16/fXIN 64/fXIN Example phase error thresholds (s) fXIN=4MHz 0 1.00 4.00 16.00 fXIN=7.2MHz 0 0.55 2.22 8.88 fXIN=8MHz 0 0.50 2.00 8.00 fXIN=10.24MHz 0 0.39 1.56 6.25 fXIN=12.8MHz 0 0.31 1.20 5.00
Bits UE0 and UE1 determine the unlock extension, or delay, before the unlock detector outputs, LDA and LDB, can change state. The extension for different reference frequenTable 5. LDA, LDB output extension
UE0 0 1 0 1 UE1 0 0 1 1 LDA, LDB output extension 4/fref 8/fref 32/fref 64/fref
cies is shown in table 5. However, if a phase-error threshold of zero is set using UL0 and UL1, no output extension occurs.
Example output extensions (ms) fref=1kHz 4.0 (typ) 8.0 32.0 64.0 fref=5kHz 0.8 1.6 6.4 (typ) 12.8 fref=12.5kHz 0.32 0.64 2.56 5.12 (typ)
Bit DZ is the dead-zone selection bit. It selects the phaseinsensitive bandwidth, or dead zone, of the phase comparator. When DZ=1, DZB mode is selected, and when DZ=0, DZA mode. DZB mode has larger dead zone than DZA mode.
Bits T0, T1 and T2 are test bits. They should be set to 0 for normal operation.
No.4160-8/11
LC7153, 7153M
Typical Application A LC7153 or LC7153M cordless telephone application circuit is shown in figure 5. The telephone is tuned to channel 1, which has a transmit VCO frequency of 46.610MHz and a receive VCO frequency of 38.975MHz.
Figure 5. American 10-channel, 46/49 MHz, cordless telephone base station
For fref = 5kHz, the divider ratios are as follows. NA= fIA RX VCO 38.975MHz = = =7795 (1E73H) fref fref 5kHz fIB TX VCO 46.610MHz = = =9322 (246AH) fref fref 5kHz fXIN 10.24MHz = 1024 (400H) 2xfref 2x5kHz
N B=
NR=
No.4160-9/11
LC7153, 7153M
The Mode 1 and Mode 2 commands are shown in tables 6 and 7, respectively, and in figures 6 and 7, respectively. Table 6. Mode 1 command
Field DA0 to DA15 DB0 to DB15 Value 1E73H 246AH PLLA divider ratio 7795 PLLB divider ratio 9322 Comment
Figure 6. Mode 1 command Table 7. Mode 2 command
Field R0 to R13 FL0, FL1 OA OB FA FB HSA, HSB HSM SB UL0, UL1 UE0, UE1 DZ T0, T1, T2 Value 0400H 00 0 0 1 1 00 0 0 or 1 11 01 1 000 Comment Reference divider ratio of 1024 Fast lock-up mode 0 OUTA and OUTB left open. 20 to 55MHz RX VCO input frequency range 20 to 55MHz TX VCO input frequency range PLLA and PLLB fast lock-up OFF Fast lock-up operating mode 0 Standby mode selection 6.25s lock/unlock detection threshold 6.4ms LDA and LDB output extension DZB dead-zone mode Test mode deselected
Figure 7. Mode 2 command
No.4160-10/11
LC7153, 7153M
Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products(including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be expor ted without obtaining the expor t license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only ; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of July, 2001. Specifications and information herein are subject to change without notice.
PS No.4160-11/11

▲Up To Search▲

Price & Availability of LC7153M

	To Download LC7153M Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .